Timing Matters

Not the way to do it

I sometimes see 8-bit CPU interfacing to memory using an output enable signal (OE) to the memory device that is generated by combining (NANDing) the read/write (R/W) line with the CPU enable (E), as shown above, in a similar way to the write enable signal (WE). This is poor design and should be avoided.

To be fair, this does generate read and write signals that are synchronised with the CPU enable (E), but that is generally not what is needed.

The CPU (eg 6809, 6502), whatever its clock speed, expects the data from memory to be maintained on the data bus for a minimum of typically 10ns after the falling edge of E (or Φ2 in the case of the 6502). This is the Read Data Hold Time on the CPU timing diagram.

The memory (ROM/RAM/EPROM/EEPROM) will tri-state its data bus outputs in a maximum of 25ns (typically, depending on the memory) after the rising edge of OE (or CS). This is the Output Hold Time on the memory timing diagram.

In addition to that, the NAND gate generating OE signal also has a Propagation Delay of a maximum of (typically) 10ns which will also delay the tri-stating of the memory data bus.

So you might think, "What's the problem? The CPU wants data maintained on the bus for at least 10ns, and the memory and control signals will maintain it for up to 35ns."

But 10ns is the minimum required and 35ns is the maximum given, with often no minimum specified in the data sheets. In practice, the data bus might have valid data on it for 20ns or 30ns, but it could be valid for less than the 10ns required and still be complying with the manufacturers’ specifications.

Indeed, some manufacturers (I'm currently looking at the datasheet for an AT28C256 EEPROM) don't specify a maximum Output Data Hold time, but instead specify a minimum of 0ns to make it clear that there is no guarantee at all of data being available on the data bus when OE (or CS for that matter) are no longer asserted.

Essentially, the poor design above relies on signal timing which is not backed up by the manufacturers' published data. But worse than that for simple 8-bit designs, it also wastes a gate that could be used elsewhere!

The Better Solution

That’s the way to do it

The better solution is simply not to gate R/W with E and to use the inverted R/W signal to directly drive OE. That way, OE is guaranteed to be valid for the minimum of the Address Hold Time of 20ns plus the propagation delay through the inverter. More than enough time for the CPU to read the data.

The Exception

Of course, there has to be an exception.

The only time you would need to generate a shorter Read Enable RD signal for an OE input is if you want something else to also access the memory on the opposite half of the CPU clock cycle.

I have done this only once, and that was to allow a video display circuit to read from video RAM simultaneously, but out of phase with, the CPU reading and writing to the video RAM. A sort of real-time cycle-by-cycle DMA. And that was over 40 years ago.